sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 174

• Manufacturer Part Number: sak-c868p-1rr
• Description: 8 - Bit Cmos Microcontroller
• Manufacturer: Infineon Technologies Corporation

5.6
The programmable Slow Down Divider (SDD) divides the PLL output clock frequency by
a factor of 1...32 which is specified via CMCON.REL. When CMCON.REL is written
during SDD operation the reload counter will output one more clock pulse with the ‘old’
frequency in order to synchronize it internally before generating the ‘new’ frequency.
Figure 5-4
SDD_clk = PLL_clk / (CMCON.REL
For a 20 MHz basic clock the on-chip logic may be run at a frequency down to 625 KHz
without an external hardware change. During Slow Down operation the whole device
(including bus interface) is clocked with the symmetrical SDD clock (see figure above).
5.6.1
Switching Control logic controls the switching mechanism itself and ensures a
continuous and glitch-free clock signal to the on-chip logic.
Note: When switch from slow down mode to PLL operation (if configured), Master clock
Switching to Slow Down operation affects frequency sensitive peripherals like serial
interfaces, timers, PWM, etc.If these units are to be operated in Slow Down mode their
Prescalers or reload values must be adapted. Please note that the reduced CPU
frequency decreases e.g. timer resolution and increases the step width e.g. for baudrate
generation. The basic clock frequency in such a case should be chosen to accommodate
the required resolutions and/or baudrates.
User’s Manual
PLL_clk
SDD_clk
will be switched to PLL clock only after PLL (pll_locked) is locked.
Slow Down Operation
Switching Between PLL Clock and SDD Clock
Slow Down Divider Operation
clk_rel=2
clk_rel=4
PLL_clk
B
+1)
Reset, Brownout and System Clock Operation
5-8
Reload Counter
rel
SDD_clk
V 1.0, 2003-01
C868