sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 192
![no-image](/images/no-image-200.jpg)
sak-c868p-1rr
Manufacturer Part Number
sak-c868p-1rr
Description
8 - Bit Cmos Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.SAK-C868P-1RR.pdf
(266 pages)
- Current page: 192 of 266
- Download datasheet (4Mb)
7.2
7.2.1
Each interrupt vector can be individually enabled or disabled by setting or clearing the
corresponding bit in the interrupt enable registers IEN0, IEN1, IEN2. Register IEN0 also
contains the global disable bit (EA), which can be cleared to disable all interrupts at once.
Generally, after reset all interrupt enable bits are set to 0. That means that the
corresponding interrupts are disabled.
The SFR IEN0 contains the enable bits for the external interrupts 0 and 1, the timer
interrupts, and the UART interrupt.
IEN0
Interrupt Enable Register 0
Field
EX0
ET0
EX1
ET1
ES
ET2
User’s Manual
AF
EA
rw
H
Interrupt Registers
Interrupt Enable Registers
AE
-
r
H
Bits
0
1
2
3
4
5
AD
ET2
rw
H
Typ Description
rw
rw
rw
rw
rw
rw
External interrupt 0 enable.
If EX0 = 0, the external interrupt 0 is disabled.
If EX0 = 1, the external interrupt 0 is enabled.
Timer 0 overflow interrupt enable.
If ET0 = 0, the timer 0 interrupt is disabled.
If ET0 = 1, the timer 0 interrupt is enabled.
External interrupt 1 enable.
If EX1 = 0, the external interrupt 1 is disabled.
If EX1 = 1, the external interrupt 1 is enabled.
Timer 1 overflow interrupt enable.
If ET1 = 0, the timer 1 interrupt is disabled.
If ET1 = 1, the timer 1 interrupt is enabled.
Serial channel (UART) interrupt enable
If ES = 0, the serial channel interrupt 0 is disabled.
If ES = 1, the serial channel interrupt 0 is enabled.
Timer 2 overflow / external reload interrupt
enable.
If ET2 = 0, the timer 2 interrupt is disabled.
If ET2 = 1, the timer 2 interrupt is enabled.
AC
ES
rw
H
7-8
AB
ET1
rw
H
AA
EX1
rw
[Reset value: 0X000000
H
A9
ET0
Interrupt System
rw
H
V 1.0, 2003-01
EX0
A8
rw
C868
H
B
]
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