sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 204

• Manufacturer Part Number: sak-c868p-1rr
• Description: 8 - Bit Cmos Microcontroller
• Manufacturer: Infineon Technologies Corporation

Field
CHE
WHE
CCU_IDLE
-
1)
2)
3)
4)
Note: Not all bits in register IS can generate an interrupt. Other status bits have been
Note: The interrupt generation is independent from the value of the bits in register IS,
Note: In compare mode (and hall mode), the timer-related interrupts are only generated
User’s Manual
During the trap state, the selected outputs are set to the passive state. The logic level driven during the passive
state is defined by the corresponding bit in register CCMCON. Bit TRPS=’1’ and TRPF=’0’ can occur if the trap
condition is no longer active but the selected synchronization has not yet taken place.
On every valid hall edge the contents of CURH is compared with the pattern on pin CCPOSx and if equal bit
CHE is set.
On every valid hall edge the contents of EXPH is compared with the pattern on pin CCPOSx. If both compares
(CURH and EXPH with CCPOSx) are not true, bit WHE (wrong hall event) is set.
Bit field MCMP is hold to ’0’ by hardware as long as CCU_IDLE = ’1’.
2)
3)
added, which have a similar structure for their set and reset actions.
e.g. the interrupt will be generated (if enabled) even if the corresponding bit is
already set. The trigger for an interrupt generation is the detection of a set
condition (by HW or SW) for the corresponding bit in register IS.
while the timer is running (TxR=1). In capture mode, the capture interrupts are also
generated while the timer T12 is stopped.
4)
Bits
4
5
6
7
Type Description
rh
rh
rh
r
Correct Hall Event
0
1
Wrong Hall Event
0
1
IDLE State
This bit is set together with bit WHE (wrong hall
event) and it has to be reset by SW.
0
1
reserved;
returns ’0’ if read; should be written with ’0’;
A transition to a correct (=expected) hall event
has not yet been detected since this bit has
been reset for the last time.
A transition to a correct (=expected) hall event
has not yet been detected.
A transition to a wrong hall event (not the
expected one) has not yet been detected since
this bit has been reset for the last time.
A transition to a wrong hall event (not the
expected one) has been detected.
No action.
Bitfield MCMP is cleared, the selected outputs
are set to passive state.
7-20
Interrupt System
V 1.0, 2003-01
C868