sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 51

• Manufacturer Part Number: sak-c868p-1rr
• Description: 8 - Bit Cmos Microcontroller
• Manufacturer: Infineon Technologies Corporation

4.4
The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to
implement special features as listed in
diagram of a typical bit latch and I/O buffer, which is the core of the I/O-ports. The bit
latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a
value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q
output of the flip-flop is placed on the internal bus in response to a "read-latch" signal
from the CPU. The level of the port pin itself is placed on the internal bus in response to
a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the
corresponding port SFR P1 and P3) activate the "read-latch" signal, while others activate
the "read-pin" signal.
Figure
placed on the internal bus in response to a "read-pin" signal from the CPU. But the
output of the flip-flop is directed internally to the hall inputs of the CCU module. The
"write to latch" and "read-latch" behave the same as in a). As output, these pins can be
used to stimulate the hall inputs of the CCU module for algorithm testing without the use
of external circuitry. As input, they can be used to verify the state of the hall input pins.
Figure 4-1
Figure 4-1
User’s Manual
a)
b)
4-1b) shows a functional diagram for pins P1.5-7. The level of the port pin is
Port 1, Port 3 Circuitry
shows a functional diagram of a port latch with alternate function.
Int. Bus
Int. Bus
Read
Latch
Write
Latch
Read
Latch
Write
Latch
Read
Read
to
to
Pin
Pin
Ports 1 and 3
D
CLK
D
CLK
Latch
Bit
Latch
Bit
Alternate
Function
Q
Q
Input
Q
Q
Alternate
Function
Output
PISELH(CCU6)
Table
4-7
4-2.
‘01’
Port
Driver
Circuit
On-Chip Peripheral Components
To CCU hall input
Figure
CCPOSx
‘00’
Port
Pin
4-1a) shows a functional
V 1.0, 2003-01
C868