cbtl12131 NXP Semiconductors, cbtl12131 Datasheet - Page 10

• Manufacturer Part Number: cbtl12131
• Description: Cbtl12131 Displayport Multiplexer For Bidirectional Video In All-in-one Computer Systems
• Manufacturer: NXP Semiconductors

Table 4.
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance; EQ = active, equalized/re-driven.
[1]
PATH_SEL HPD_B_FLT
Remark: Signal ordering between Port B and Port D is inverted in order to achieve proper signal-to-pin mapping in accordance with sink side status of connector at Port B.
0
0
1
Inputs
Main Link signal mappings
0
1
X
ML_C_0P
ML_C_0N
ML_C_1P
ML_C_1N
ML_C_2P
ML_C_2N
ML_C_3P
ML_C_3N
ML_C_0P
ML_C_0N
ML_C_1P
ML_C_1N
ML_C_2P
ML_C_2N
ML_C_3P
ML_C_3N
ML_C_0P
ML_C_0N
ML_C_1P
ML_C_1N
ML_C_2P
ML_C_2N
ML_C_3P
ML_C_3N
Port C - Port D
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ML_D_0P
ML_D_0N
ML_D_1P
ML_D_1N
ML_D_2P
ML_D_2N
ML_D_3P
ML_D_3N
ML_D_0P
ML_D_0N
ML_D_1P
ML_D_1N
ML_D_2P
ML_D_2N
ML_D_3P
ML_D_3N
ML_D_0P
ML_D_0N
ML_D_1P
ML_D_1N
ML_D_2P
ML_D_2N
ML_D_3P
ML_D_3N
ML_A_0N
ML_A_1N
ML_A_2N
ML_A_3N
ML_A_0N
ML_A_1N
ML_A_2N
ML_A_3N
ML_A_0N
ML_A_1N
ML_A_2N
ML_A_3N
ML_A_0P
ML_A_1P
ML_A_2P
ML_A_3P
ML_A_0P
ML_A_1P
ML_A_2P
ML_A_3P
ML_A_0P
ML_A_1P
ML_A_2P
ML_A_3P
Port A - Port B
Channels
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ML_B_0P
ML_B_0N
ML_B_1P
ML_B_1N
ML_B_2P
ML_B_2N
ML_B_3P
ML_B_3N
ML_B_0P
ML_B_0N
ML_B_1P
ML_B_1N
ML_B_2P
ML_B_2N
ML_B_3P
ML_B_3N
ML_B_0P
ML_B_0N
ML_B_1P
ML_B_1N
ML_B_2P
ML_B_2N
ML_B_3P
ML_B_3N
ML_B_0P
ML_B_0N
ML_B_1P
ML_B_1N
ML_B_2P
ML_B_2N
ML_B_3P
ML_B_3N
ML_B_0P
ML_B_0N
ML_B_1P
ML_B_1N
ML_B_2P
ML_B_2N
ML_B_3P
ML_B_3N
ML_B_0P
ML_B_0N
ML_B_1P
ML_B_1N
ML_B_2P
ML_B_2N
ML_B_3P
ML_B_3N
Port B - Port D
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
EQ
EQ
EQ
EQ
EQ
EQ
EQ
EQ
ML_D_3N
ML_D_3P
ML_D_2N
ML_D_2P
ML_D_1N
ML_D_1P
ML_D_0N
ML_D_0P
ML_D_3N
ML_D_3P
ML_D_2N
ML_D_2P
ML_D_1N
ML_D_1P
ML_D_0N
ML_D_0P
ML_D_3N
ML_D_3P
ML_D_2N
ML_D_2P
ML_D_1N
ML_D_1P
ML_D_0N
ML_D_0P
[1]
Comment (all other ports
shall be mutually isolated)
Normal mode;
internal display only
Normal mode with
dual display
External source mode