cbtl12131 NXP Semiconductors, cbtl12131 Datasheet - Page 9

• Manufacturer Part Number: cbtl12131
• Description: Cbtl12131 Displayport Multiplexer For Bidirectional Video In All-in-one Computer Systems
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
Table 3.
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance.
CBTL12131
Product data sheet
PATH_SEL
0
0
1
1
Inputs
Main Link channel configuration
HPD_B_FLT
7.1 General
7.2 Main Link DisplayPort switches/multiplexers
0
1
0
1
The CBTL12131 is a high-bandwidth DisplayPort channel switching device designed for
use in all-in-one computers. It contains high-bandwidth switches arranged between four
Ports (A through D) to allow two different channel topologies, where each channel
comprises a Main Link (ML), AUX and HPD path for comprehensive DisplayPort channel
switching. One can select between two basic configurations: either Ports A and C are
connected to Ports B and D respectively, or Port B is connected to Port D while Ports A
and C are high-impedance. In addition, the CBTL12131 includes circuitry to assist in
detection and configuration of Port B designated as the port facing the external
DisplayPort connector. This section describes these functional blocks in detail.
The Main Link path topology provides for four differential pairs in each Port, and an
equalizer for each differential pair in the path from Port B to Port D, as shown in
The Main Link switches are operated by CMOS input PATH_SEL and further qualified by
the state of internally derived signal HPD_B_FLT (see
PATH_SEL is LOW, Ports C and D are mutually connected, Ports A and B are mutually
connected only when HPD_B_FLT is HIGH, and the equalizer is turned off (isolating).
When PATH_SEL is HIGH, Ports A and C are disconnected (high-impedance) and Port D
is connected to Port B via the equalizer. The equalizer can by bypassed or configured by
quinary input EQ5 to any of five equalizer settings (including a flat response) depending
on specific application conditions. For details on the Equalizer function, please refer to
Section
Fig 5.
PATH_SEL = 0 and
HPD_B_FLT = 1: pass
else: off
PATH_SEL = 0: pass
PATH_SEL = 1: off
Port C - Port D
7.7.
Main Link channel topology
high-Z
high-Z
ACT
ACT
ML port C
ML port A
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
Port A - Port B
Channels
high-Z
high-Z
high-Z
ACT
EQ5
PL5
LV5
Port B - Port D
DisplayPort multiplexer for bidirectional video
high-Z
high-Z
ACT
ACT
EQ
EQ output disabled/no load when PATH_SEL = 0
Section 7.6
Comment
Normal mode; internal display only
Normal mode with dual display
External source mode with internal
display not yet asserting HPD
External source mode with internal
display asserting HPD
ML port D
ML port B
CBTL12131
for details). When
© NXP B.V. 2011. All rights reserved.
002aae677
Figure
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5.