cbtl12131 NXP Semiconductors, cbtl12131 Datasheet - Page 7

• Manufacturer Part Number: cbtl12131
• Description: Cbtl12131 Displayport Multiplexer For Bidirectional Video In All-in-one Computer Systems
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
CBTL12131
Product data sheet
Symbol
Port A terminals
ML_A_0P
ML_A_0N
ML_A_1P
ML_A_1N
ML_A_2P
ML_A_2N
ML_A_3P
ML_A_3N
AUX_A_P
AUX_A_N
DDC_A_0
DDC_A_1
HPD_A
Port B terminals
ML_B_0P
ML_B_0N
ML_B_1P
ML_B_1N
ML_B_2P
ML_B_2N
ML_B_3P
ML_B_3N
AUX_B_P
AUX_B_N
HPD_B
Pin description
K6
Pin
K7
J7
K8
J8
K9
J9
K10
J10
H10
H9
G10
G9
A7
B7
A8
B8
A9
B9
A10
B10
C10
C9
A6
Type
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
3.3 V LVTTL
single-ended output
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
differential port terminal
3.3 V bidirectional
LVTTL I/O with high-Z
state
…continued
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
Description
Four high-speed differential pairs for DisplayPort Main Link signals,
Port A. Designated as port facing the GPU for external video. Port A
will be exclusively connected to Port B when PATH_SEL = LOW, and
will be high-impedance when PATH_SEL = HIGH.
High-speed differential pair for DisplayPort AUX signals, Port A.
These terminals are active when DDC_AUX_SEL = LOW only;
when DDC_AUX_SEL = HIGH, these are high-impedance.
Port A terminal intended for AUX AC coupling capacitor bypass.
These terminals are active when DDC_AUX_SEL = HIGH only;
when DDC_AUX_SEL = LOW, these are high-impedance.
3.3 V LVTTL HPD output for Port A. When PATH_SEL = LOW, this
output follows the state of HPD_B (from external DP or ++DP sink).
When PATH_SEL = HIGH, this output is always LOW.
Four high-speed differential pairs for DisplayPort Main Link signals,
Port B. Designated as port facing the external DP connector. Port B
will be exclusively connected to Port A when PATH_SEL = LOW and
HPD_B_FLT = HIGH, and will be exclusively connected to Port D
when PATH_SEL = HIGH. When PATH_SEL = HIGH, the signal
ordering and association to Port D ML signals is automatically
corrected by internal routing, to map to the DP connector's inverted
signal ordering for a DP sink-side connector.
High-speed differential pair for DisplayPort AUX signals, Port B.
HPD input with 5 V tolerance or output for Port B, to be connected to
the external DP connector. When PATH_SEL = LOW, HPD_B is
configured as input (from external DP or ++DP sink). When
PATH_SEL = HIGH, HPD_B is configured as output and follows the
state of HPD_D (from internal sink), to be connected via DP
connector to an external DP source.
DisplayPort multiplexer for bidirectional video
CBTL12131
© NXP B.V. 2011. All rights reserved.
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