tea1202ts NXP Semiconductors, tea1202ts Datasheet - Page 10

• Manufacturer Part Number: tea1202ts
• Description: Battery Power Unit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.9
If an external high-frequency clock or a HIGH level is
applied to pin SYNC/PWM, the TEA1202TS will use PWM
regulation independent of the load applied.
In the event a high-frequency clock is applied, the
switching frequency in the PWM mode will be exactly that
frequency divided by 22. In the PWM mode the quiescent
current of the device increases.
In the event that no external synchronization or PWM
mode selection is necessary, pin SYNC/PWM must be
connected to ground.
8.10
In general, an input voltage exceeding the specified range
is not recommended since instability may occur. There are
two exceptions:
8.11
The low drop-out voltage regulators are functionally equal
apart from the shut-down mechanism: LDO2 can be
controlled separately by pin SHDWN2, while LDO1 is
controlled by pin SHDWN0 like the DC-to-DC converter.
The input voltage of each LDO must be 250 mV (at
I
specification on e.g. ripple rejection. However, the parts
will function like an LDO down to a margin of 45 mV (at
I
drop-out voltage. At a lower margin between input and
output, the LDOs will behave like a resistor.
2002 Mar 14
LDO
LDO
Upconversion: at an input voltage higher than the target
output voltage, but up to 5.5 V, the converter will stop
switching and the external Schottky diode will take over.
The output voltage will equal the input voltage minus the
diode voltage drop. Since all current flows through the
external diode in this situation, the current limiting
function is not active.
In the PWM mode, the P-type power MOSFET is always
on when the input voltage exceeds the target output
voltage. The internal synchronous rectifier ensures that
the inductor current does not fall below zero. As a result,
the achieved efficiency is higher in this situation than
standard PWM-controlled converters achieve.
Downconversion: when the input voltage is lower than
the target output voltage, but higher than 2.2 V, the
P-type power MOSFET will stay conducting resulting in
an output voltage being equal to the input voltage minus
some resistive voltage drop. The current limiting
function remains active.
0.95 V starting power unit
= 50 mA) higher than its output voltage to achieve full
= 50 mA) between input and output: the so-called
External synchronization and PWM-only mode
Behaviour at input voltage exceeding the
specified range
Low drop-out voltage regulators
10
Both LDOs are protected from high temperature
(see Section 8.7).
Next to normal LDO functions, both regulators can be
switched off or can be used as switches. Each regulator
will act as a low-ohmic switch in the on-state when its
feedback input is connected to ground. When the
feedback input is higher than 2 V, the regulator will make
its power FET high-ohmic. So the feedback inputs of the
regulators can be used as digital inputs which make the
LDOs behave as switches.
8.12
The low battery detector is an autonomous circuit which
can work at an input voltage down to 0.90 V. It is always
on, even when all other blocks are in the shut-down mode.
The detector has two inputs: the input on pin LBI1 is tuned
to accept a single-cell NiCd or NiMH battery voltage
directly, while the input on pin LBI2 can detect a two-cell
NiCd or NiMH battery voltage or higher voltage. The
detection level of the input on pin LBI2 can be set by using
a voltage divider between the battery voltage, pin LBI2 and
ground. Hysteresis is included for proper operating.
Furthermore, a capacitor of 10 nF (typical value) must be
connected between pin LBI1 and ground when the input
on pin LBI2 is used.
The output of the low battery detector on pin LBO is an
open-collector output. The output is high (i.e. no current is
sunk by the collector) when the input voltage of the
detector is below the lower detection level.
Low battery detector
Preliminary specification
TEA1202TS