tea1202ts NXP Semiconductors, tea1202ts Datasheet - Page 14

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tea1202ts

Manufacturer Part Number
tea1202ts
Description
Battery Power Unit
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
Notes
1. The undervoltage lockout level shows wide specification limits since it decreases at increasing temperature. When
2. When V
3. The quiescent current is specified as the current in to pin UPOUT/DNIN (pin 4) in the upconversion configuration at
4. The current limit is defined by resistor R10. This resistor must have 1% accuracy.
5. The specified efficiency is valid when using an output capacitor having an ESR of 0.1
6. The specified start-up time is the time between the connection of a 1.20 V input voltage source and the moment the
7. V
8. Take care regarding total dissipation if output current I
9. The drop-out voltage is defined as the voltage between the input and the output of the LDO when the output voltage
10. The output voltage of each LDO is defined by external feedback resistors. These resistors must have 1% accuracy.
11.
12.
13. Measured with a sine wave at f
2002 Mar 14
General characteristics
V
I
T
T
q
SYMBOL
amb
max
ref
0.95 V starting power unit
the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore
the correct operation of this function is guaranteed over the whole temperature range. The undervoltage lockout level
is measured at pin UPOUT/DNIN.
conducting (duty factor is 100%), resulting in V
V
with an ESR of 0.05
output reaches 3.30 V. The output capacitance equals 100 F, the inductance equals 6.8 H and no load is present.
of the device will increase.
has dropped 100 mV below its nominal value. The drop-out voltage is measured while the LDO input voltage is
decreasing.
I
4
V
V
= 1.20 V and V
is the voltage at pin UPOUT/DNIN. If the applied HIGH-level voltage is less than V
line
load
=
=
I(dwn)
----------------------------
V
--------------------------------- -
V
reference voltage
quiescent current at
pin UPOUT/DNIN
ambient temperature
internal temperature for cut-off
LDO
LDO
V
is lower than the target output voltage but higher than 2.2 V, the P-type power MOSFET will remain
LDO
V
LDO
O
V
I
= 3.30 V, using L1 = 6.8 H, R1 = 150 k and R2 = 91 k .
LDO
PARAMETER
I
100
and a sufficient saturation current level.
100
%/V.
%/mA.
i
= 100 Hz to 1 MHz, V
all blocks operating
O(dwn)
CONDITIONS
following V
i
LDO
14
= 100 mV (RMS), C
> 50 mA and drop voltage V
I(dwn)
.
L
1.165
150
= 2.2 F and I
20
MIN.
4
1.190
270
+25
160
drop
TYP.
and an inductor of 6.8 H
1 V, the quiescent current
LDO
> 2 V.
Preliminary specification
TEA1202TS
= 10 mA.
1.215
+80
170
MAX.
V
C
C
A
UNIT

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