lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 17

• Manufacturer Part Number: lm4935rlx
• Description: Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
• Manufacturer: National Semiconductor Corporation

11.0 System Control
Method 1. I
11.1 I
In I
signals need a pull-up resistor according to I
11.2 I
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can
only be changed when SCL is LOW.
11.3 I
START and STOP bits classify the beginning and the end of the I
transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH
while SCL is HIGH. The I
condition and free after STOP condition. During data transmission, I
START and repeated START conditions are equivalent, function-wise.
11.4 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data
has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9
pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been
received.
After the START condition, the I
is a data direction bit (R/W). The LM4935 address is 0011010
READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected
register.
Register changes take an effect at the SCL rising edge during the last ACK from slave.
2
C mode the LM4935 pin SCL is used for the I
2
2
2
C SIGNALS
C DATA VALIDITY
C START AND STOP CONDITIONS
2
C Compatible Interface
2
C master always generates START and STOP bits. The I
2
C master sends a chip address. This address is seven bits long followed by an eighth bit which
2
C specification. The I
2
I
C clock SCL and the pin SDA is used for the I
2
C Signals: Data Validity
I
2
C Chip Address
2
. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
17
2
C slave address for LM4935 is 0011010
2
C master can generate repeated START conditions. First
2
C session. START condition is defined as SDA signal
2
C bus is considered to be busy after START
201341Q1
201341Q2
201341Q3
2
C data signal SDA. Both these
2
.
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