lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 62

• Manufacturer Part Number: lm4935rlx
• Description: Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
• Manufacturer: National Semiconductor Corporation

12.0 Status & Control Registers
(Continued)
2
Only the 8 MSBS [11:4] from the 12 bits of SAR output data can be read back using the I
C interface.
The SPI interface can be used to access all 12 bits of the SAR output data. In this case, GPIO2 should be set to SAR_SDO by
setting GPIO_SEL in register (0x1Ah). The SAR channel selected by SAR_CH_SEL in the GPIO register is then output onto
GPIO2 as follows:
20134108
FIGURE 14. SPI SAR Read Transaction (GPIO2 set to SAR_SDO)
In applications where the 8 MSBS [11:4] from the SAR output data is enough resolution, GPIO2 should be set to SPI_SDO by
setting GPIO_SEL in register (0x1Ah). The SAR data is then output on GPIO2 as follows:
20134107
FIGURE 15. SPI SAR Read Transaction (GPIO2 set to SPI_SDO)
If the user performs a write to the GPIO register the changes will not take effect until the next SPI operation so SAR data can be
read while the next channel is being selected. The SAR data is sampled at the start of the SPI transaction to ensure that the data
is stable during the read operation.
2
All 12 bits of the SAR output data for up to 2 SAR channels can be read back simultaneously through the bi-directional I
S
interface. This is accomplished by setting I2S_SDO_DATA (bit [7:6] of (0x19h)) to the desired SAR channel(s).
2
As mentioned previously in the Digital Audio Data Formats section, when SAR SDO is passed to the I
S bus, the SAR SDO’s
MSB is aligned with the MSB of I2S_SDO.
www.national.com
62