lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 55

• Manufacturer Part Number: lm4935rlx
• Description: Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
• Manufacturer: National Semiconductor Corporation

Bits
1:0
7:6
2
3
4
5
12.0 Status & Control Registers
12.31 AUDIO INTERFACE CONFIGURATION REGISTER
This register is used to control the configuration of the audio data interfaces.
AUDIO_IF_MODE
PCM_SYNC_MS
I2S_SDO_DATA
PCM_CLK_MS
I2S_CLK_MS
I2S_WS_MS
Field
Selects the function of the 6 audio interface IOs.
If set the I
If set the I
If set the PCM_SYNC is produced by the LM4935 and the relevant pin will be an output.
If set the PCM_CLK is produced by the LM4935 and the relevant pin will be an output.
The two ADCs on the LM4935 can both be read via the isochronous I2S interface. The most recent
valid sample is output from the following source: (Please refer to the GPIO configuration register
(0x1Ah) for more information on SAR_CH_SEL)
AUDIO_IF_MODE
00
01
10
11
2
2
2
2
2
2
S_WS is produced by the LM4935 and the I
S_CLK is produced by the LM4935 and the I
I2S_SDO_DATA
TABLE 31. AUDIO_IF (0x19h)
00
01
10
11
CLK pin
2
2
2
2
PCM
PCM
I2S_
CLK
CLK
CLK
CLK
I
I
2
2
S
S
(Continued)
55
WS pin
SYNC
SYNC
PCM
PCM
I2S_
WS
WS
I
I
2
2
S
S
Description
SDI pin
PCM
I2S_
SDI
SDI
SDI
I
I
2
2
-
S
S
SAR VSAR 1
SAR VSAR 2
2
AUDIO ADC
2
S_WS pin will be an output.
S_CLK pin will be an output.
A_V
LEFT
DD
SDO pin
/2
PCM
PCM
PCM
SDO
SDO
SDO
SDO
I2S_
I
2
S
GPIO_1
GPIO
GPIO
GPIO
PCM
CLK
pin
1
1
1
SAR_CH_SEL
SAR_CH_SEL
SAR_CH_SEL
SAR_CH_SEL
RIGHT
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GPIO_2
SYNC
GPIO
GPIO
GPIO
PCM
pin
2
2
2