lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 57

• Manufacturer Part Number: lm4935rlx
• Description: Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
• Manufacturer: National Semiconductor Corporation

Bits
12.0 Status & Control Registers
12.33 GPIO CONFIGURATION REGISTER
This register is used to control the GPIO system.
2:0
4:3
Note 30: The left justified I
5
6
7
SAR_CH_SEL
PCM_LONG
GPIO_DATA
I2S_MODE
GPIO_SEL
Field
2
S mode is similar to normal I
This sets the function of the GPIOs when the Audio Interface is not using them.
Setting GPIO_SEL = “010” with the GPIO_TEST_MODE bit (register 0X26h) set configures the
GPIOs for digital mic operation. With this setting, GPI01 will output VADC_CLK_OUT to provide a
clock for the digital mic. GPIO2 will accept digital mic data. GPIO1’s LS_AMP_ENABLE setting will
be logic high whenever the loudspeaker amplifier is enabled. This is useful for enabling an external
amplifier for stereo loudspeaker applications.
This field selects the SAR output channel for the 2nd (Right) I
GPIO2.
If set the I2S operates in left justified mode (sometimes referred to as DSP mode). See example
below. (Note 30)
If set the PCM interface uses LONG frame sync which is essentially an inverted short frame sync.
If GPIO_SEL is set to GPIO_DATA then the content of this field is passed to GPIO1 as an output.
FIGURE 12. I
SAR_CH_SEL
GPIO_SEL
000
001
010
100
101
011
110
111
00
01
10
11
2
2
2
2
2
2
2
2
2
2
2
2
2
S other than there is no delay between a change in WS to the MSB:
2
S Serial Data Format (Left Justified Mode)
TABLE 32. GPIO (0x1Ah)
(Continued)
57
LS_AMP_ENABLE
LS_AMP_ENABLE
GPIO_DATA
GPIO_DATA
Description
READABLE
READABLE
GPIO 1
0
0
D_V
Selected Channel
DD
2
S channel or for SAR_SDO via
VSAR_1
VSAR_2
A_V
/2 or BB_V
DD
/2
DD
SAR_SDO
SAR_SDO
SAR_SDO
SPI_SDO
SPI_SDO
SPI_SDO
SPI_SDO
GPIO 2
0
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