lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 23

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lm4935rlx

Manufacturer Part Number
lm4935rlx
Description
Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
Manufacturer
National Semiconductor Corporation
Datasheet
Bits
12.0 Status & Control Registers
12.2 CLOCKS CONFIGURATION REGISTER
This register is used to control the clocks throughout the chip.
7:2
0
1
DAC_CLK
ADC_CLK
R_DIV
Field
Selects the clock to be used by the audio DAC system.
Selects the clock to be used by the audio ADC system.
Programs the R divider (divides from an expected 12.000 MHz input).
DAC_CLK
ADC_CLK
13 to 61
R_DIV
TABLE 3. CLOCKS (0x01h)
10
11
12
62
63
0
1
0
1
0
1
2
3
4
5
6
7
8
9
(Continued)
23
Description
PLL Input (MCLK or I2S_CLK)
Audio ADC Input Source
DAC Input Source
Divide Value
PLL Output
PLL Output
Bypass
Bypass
7 to 31
MCLK
31.5
1.5
2.5
3.5
4.5
5.5
6.5
32
2
3
4
5
6
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