DM7473N Fairchild Semiconductor, DM7473N Datasheet
DM7473N
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7473N
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DM7473N Summary of contents
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... J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the Ordering Code: Order Number Package Number DM7473N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram © 2001 Fairchild Semiconductor Corporation negative transition of the clock, the data from the master is transferred to the slave ...
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Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...