DM7476N Fairchild Semiconductor, DM7476N Datasheet

DM7476N

Manufacturer Part Number

DM7476N

Description

IC FLIP FLOP DUAL J-K 16DIP

Manufacturer

Fairchild Semiconductor

Series

7400r

Type

JK Typer

Datasheet

1.DM7476N.pdf (4 pages)

Specifications of DM7476N

Function

Set(Preset) and Reset

Output Type

Differential

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

15MHz

Delay Time - Propagation

25ns

Trigger Type

Positive Edge

Current - Output High, Low

400µA, 16mA

Voltage - Supply

4.75 V ~ 5.25 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Through Hole

Package / Case

16-DIP (0.300", 7.62mm)

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

7476

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

DM7476N

Manufacturer:

Quantity:

6 231

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DM7476N

DM7476

Dual Master-Slave J-K Flip-Flops with

Clear, Preset, and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop after a complete clock

pulse. While the clock is LOW the slave is isolated from the

master. On the positive transition of the clock, the data

from the J and K inputs is transferred to the master. While

the clock is HIGH the J and K inputs are disabled. On the

Ordering Code:

Connection Diagram

Order Number

Package Number

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006528

negative transition of the clock, the data from the master is

transferred to the slave. The logic state of J and K inputs

must not be allowed to change while the clock is HIGH.

The data is transferred to the outputs on the falling edge of

the clock pulse. A LOW logic level on the preset or clear

inputs will set or reset the outputs regardless of the logic

levels of the other inputs.

Function Table

Toggle

Note 1: This configuration is nonstable; that is, it will not persist when the

preset and/or clear inputs return to their inactive (HIGH) level.

LOW Logic Level

Either LOW or HIGH Logic Level

HIGH Logic Level

the clock is HIGH. Data is transferred to the outputs on the falling

edge of the clock pulse.

established.

each complete active HIGH level clock pulse.

Positive pulse data. The J and K inputs must be held constant while

The output logic level before the indicated input conditions were

Package Description

Each output changes to the complement of its previous level on

CLR

Inputs

CLK

September 1986

Revised February 2000

www.fairchildsemi.com

(Note 1)

Outputs

Toggle

(Note 1)

Related parts for DM7476N

DM7476N Summary of contents

Page 1

... J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the Ordering Code: Order Number Package Number DM7476N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation negative transition of the clock, the data from the master is transferred to the slave ...

Page 2

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 3

Switching Characteristics and Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...

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