DM74S74N Fairchild Semiconductor, DM74S74N Datasheet
DM74S74N
Manufacturer Part Number
DM74S74N
Description
IC F/F DUAL POS-EDGE-TRIG 14-DIP
Manufacturer
Fairchild Semiconductor
Series
74Sr
Type
D-Typer
Datasheet
1.DM74S74N.pdf
(5 pages)
Specifications of DM74S74N
Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
65MHz
Delay Time - Propagation
12ns
Trigger Type
Positive Edge
Current - Output High, Low
1mA, 20mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
14-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74S74
74S74N
74S74N
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© 2000 Fairchild Semiconductor Corporation
DM74S74M
DM74S74N
DM74S74
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the preset
or clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006457
Function Table
H
X
L
*
Q
0
preset and/or clear inputs return to its inactive (HIGH) level.
established.
This configuration is nonstable; that is, it will not persist when either the
LOW Logic Level
Positive-going Transition
Either LOW or HIGH Logic Level
HIGH Logic Level
PR
The output logic level of Q before the indicated input conditions were
H
H
H
H
L
L
Package Description
CLR
H
H
H
H
L
L
Inputs
CLK
X
X
X
L
August 1986
Revised April 2000
D
H
X
X
X
X
L
www.fairchildsemi.com
Q
H*
Q
H
H
L
L
0
Outputs
Q
H*
Q
H
H
L
L
0
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Datasheet:
DM74S74N Summary of contents
Page 1
... Package Number DM74S74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74S74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...
Page 2
Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
Page 3
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter V Input Clamp Voltage HIGH Level V OH Output Voltage V V LOW Level V OL Output Voltage V I Input Current @ ...
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 4 ...
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...