dm96ls02 Fairchild Semiconductor, dm96ls02 Datasheet
dm96ls02
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dm96ls02 Summary of contents
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... The pulse width is set by an external resistor and capacitor. Resistor values up to 1.0 M reduce required capacitor values. Hysteresis is pro- vided on both trigger inputs of the DM96LS02 for increased noise immunity. Ordering Code: Order Number Package Number ...
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... The minimum negative pulse width into I0 is 8.0 ns; the X minimum positive pulse width into ns. 2. Input signals to the DM96LS02 exhibiting slow or noisy transitions can use either trigger as both are Schmitt trig- gers. 3. When non-retriggerable operation is required, i.e., when input triggers are to be ignored during quasi-stable state, input latching is used to inhibit retriggering ...
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Operation Notes (continued) Typical Performance Characteristics Output t vs. R and Delay Time vs Triggering Truth Table Pin Numbers 5(11) 4(12) 3(13 ...
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Typical Performance Characteristics (continued) Normalized t vs Input Pulse f 100 kHz Amp 3.0V Width 100 www.fairchildsemi.com Pulse Width vs. R FIGURE ...
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Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
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Switching Characteristics V 5.0V Symbol Parameter t Propagation Delay PLH Propagation Delay PHL Propagation Delay PLH Propagation Delay PHL ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...