dm96ls02 Fairchild Semiconductor, dm96ls02 Datasheet

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dm96ls02

Manufacturer Part Number
dm96ls02
Description
Dual Retriggerable Resettable Monostable Multivibrator
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor Corporation
DM96LS02M
DM96LS02N
DM96LS02
Dual Retriggerable Resettable Monostable Multivibrator
General Description
The DM96LS02 is a dual retriggerable and resettable
monostable multivibrator. The one-shot provides excep-
tionally wide delay range, pulse width stability, predictable
accuracy and immunity to noise. The pulse width is set by
an external resistor and capacitor. Resistor values up to 1.0
M
vided on both trigger inputs of the DM96LS02 for increased
noise immunity.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
V
GND
Pin Descriptions
Order Number
CC
reduce required capacitor values. Hysteresis is pro-
Names
Pin 16
Pin 8
Pin
I0
I0
I1
C
Q
Q
D
Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
True Pulse Output
Complementary Pulse Output
Package Number
M16A
N16E
Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS009816
Features
Connection Diagram
Required timing capacitance reduced by factors of 10 to
100 over conventional designs
Broad timing resistor range—1.0 k to 2.0 M
Output Pulse Width is variable over a 2000:1 range by
resistor control
Propagation delay of 35 ns
0.3V hysteresis on trigger inputs
Output pulse width independent of duty cycle
35 ns to
Package Description
output pulse width range
October 1988
Revised March 2000
www.fairchildsemi.com

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dm96ls02 Summary of contents

Page 1

... The pulse width is set by an external resistor and capacitor. Resistor values up to 1.0 M reduce required capacitor values. Hysteresis is pro- vided on both trigger inputs of the DM96LS02 for increased noise immunity. Ordering Code: Order Number Package Number ...

Page 2

... The minimum negative pulse width into I0 is 8.0 ns; the X minimum positive pulse width into ns. 2. Input signals to the DM96LS02 exhibiting slow or noisy transitions can use either trigger as both are Schmitt trig- gers. 3. When non-retriggerable operation is required, i.e., when input triggers are to be ignored during quasi-stable state, input latching is used to inhibit retriggering ...

Page 3

Operation Notes (continued) Typical Performance Characteristics Output t vs. R and Delay Time vs Triggering Truth Table Pin Numbers 5(11) 4(12) 3(13 ...

Page 4

Typical Performance Characteristics (continued) Normalized t vs Input Pulse f 100 kHz Amp 3.0V Width 100 www.fairchildsemi.com Pulse Width vs. R FIGURE ...

Page 5

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 6

Switching Characteristics V 5.0V Symbol Parameter t Propagation Delay PLH Propagation Delay PHL Propagation Delay PLH Propagation Delay PHL ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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