fxl3sd206 Fairchild Semiconductor, fxl3sd206 Datasheet - Page 6

• Manufacturer Part Number: fxl3sd206
• Description: Fxl3sd206 ? Level Shifting Voltage Translator
• Manufacturer: Fairchild Semiconductor

© 2009 Fairchild Semiconductor Corporation
FXL3SD206 • Rev. 1.0.0
Application Information
Power-Up / Power-Down Sequencing
FXL translators offer an advantage in that any V
be powered up first. This benefit derives from the chip
design. When VDDA or both VDD_HI and VDD_LO pins
are at 0 volts, outputs are in a high-impedance state
(see
multiplexer, the device allows the unselected port to
remain in a high-impedance state for power saving. The
control inputs (OE, CH_SEL, VDD_SEL) are designed
to track VDD_CON. An external pull-down resistor tying
OE to GND should be used to ensure that bus
contention, excessive current, or oscillations do not
occur during power-up/power-down. The size of the
pull-down resistor is based upon the current-sinking
capability of the device driving the OE pin.
During normal operation, V
equal to V
V
Table 1.
DD_LO
VDDA
OFF
ON
ON
ON
ON
Power
may exceed V
DD_LO
Power-Up Operation
Up
Don’t Care
VDD_HI
. During power-up or power-down,
OFF
OFF
ON
ON
Operation
DD_HI
without damaging the device.
DD_HI
must be greater than or
table
Don’t Care
VDD_LO
OFF
OFF
ON
ON
below). As a
DD
may
VDD_SEL
Don’t Care
Don’t Care
HIGH
HIGH
HIGH
LOW
LOW
LOW
6
The recommended power-up sequence is:
1.
2.
3.
4.
The recommended the power-down sequence is:
1.
2.
3.
4.
Apply the power to the first V
Apply the power to the second V
Set the CH_SEL and VDD_SEL pin according to
the application.
Drive the OE input high to enable the device.
Drive the OE input low to disable the device.
Remove the setting of CH_SEL and VDD_SEL pin.
Remove power from either V
Remove power from other V
Enabled, Reference to VDD_LO
Enabled, Reference to VDD_LO
Enabled, Reference to VDD_HI
Enabled, Reference to VDD_HI
Port B or C Outputs
High Impedance
High Impedance
High Impedance
High Impedance
DD
DD
DD
.
.
.
DD
.
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