psd813f2v STMicroelectronics, psd813f2v Datasheet - Page 18

• Manufacturer Part Number: psd813f2v
• Description: Flash In-system Programmable Isp Peripherals For8-bits Mcus, 3v
• Manufacturer: STMicroelectronics

PSD813F2V, PSD854F2V
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6. I/O Port Latched Address Output Assignments (Note1)
Note: 1. See the section entitled
Table 7. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
18/109
8051XA (8-bit)
80C251 (page mode)
All other 8-bit multiplexed
8-bit non-multiplexed bus
Data In
Control
Data Out
Direction
Drive Select
Input Macrocell
Enable Out
Output Macrocells
AB
Output Macrocells
BC
Mask Macrocells AB
Mask Macrocells BC
Primary Flash
Protection
Secondary Flash
memory Protection
JTAG Enable
PMMR0
PMMR2
Page
VM
Register Name
2. N/A = Not Applicable
6
shows the offset addresses to the PSD
MCU
00
02
04
06
08
0A
0C
20
22
Port A
I/O PORTS, page
01
03
05
07
09
0B
0D
20
21
22
23
Port B
N/A
N/A
Address a3-a0
N/A
Port A (3:0)
10
12
14
16
18
1A
21
23
Port C
51, on how to enable the Latched Address Output function.
Doc ID 10552 Rev 3
Port A
11
13
15
17
1B
Port D Other
Address a7-a4
N/A
Address a7-a4
N/A
Port A (7:4)
C0
C2
C7
B0
B4
E0
E2
Table
in CSIOP space. The following section gives a
more detailed description.
1
Reads Port pin as input, MCU I/O input mode
Selects mode between MCU I/O or Address Out
Stores data for output to Port pins, MCU I/O
output mode
Configures Port pin as input or output
Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.
Reads Input Macrocells
Reads the status of the output enable to the I/O
Port driver
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Blocks writing to the Output Macrocells AB
Blocks writing to the Output Macrocells BC
Read only – Primary Flash Sector Protection
Read only – PSD Security and Secondary Flash
memory Sector Protection
Enables JTAG Port
Power Management Register 0
Power Management Register 2
Page Register
Places PSD memory areas in Program and/or
Data space on an individual basis.
7
provides brief descriptions of the registers
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (3:0)
Description
Port B
N/A
Address a15-a12
Address a7-a4
Address a7-a4
Port B (7:4)