psd813f2v STMicroelectronics, psd813f2v Datasheet - Page 96

• Manufacturer Part Number: psd813f2v
• Description: Flash In-system Programmable Isp Peripherals For8-bits Mcus, 3v
• Manufacturer: STMicroelectronics

PSD813F2V, PSD854F2V
Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
Figure 49. Reset (RESET) Timing
Table 65. Reset (RESET) Timing (5V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
Table 66. Reset (RESET) Timing (3V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
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t
t
t
t
t
t
t
t
t
t
t
WLQV–PA
DVQV–PA
WHQZ–PA
NLNH
NLNH–PO
NLNH–A
OPR
NLNH
NLNH–PO
NLNH–A
OPR
Symbol
Symbol
Symbol
V
RESET
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
CC
WR to Data Propagation Delay
Data to Port A Data Propagation Delay
WR Invalid to Port A Tri-state
RESET Active Low Time
Power On Reset Active Low Time
Warm Reset (on the PSD834Fx)
RESET High to Operational Device
RESET Active Low Time
Power On Reset Active Low Time
Warm Reset (on the PSD834Fx)
RESET High to Operational Device
Power-On Reset
V
t NLNH-PO
CC
Parameter
(min)
Parameter
Parameter
1
1
Doc ID 10552 Rev 3
2
2
t OPR
Conditions
(Note
(Note
(Note
Conditions
Conditions
2
5
2
)
)
)
Min Max Min Max Min Max
-12
42
38
33
Warm Reset
t NLNH-A
Min
150
Min
300
t NLNH
25
25
1
1
-15
45
40
33
Max
Max
120
300
t OPR
-20
AI02866b
55
45
35
Unit
Unit
Unit
ms
ms
ns
ns
ns
ns
μs
ns
ns
μs
ns