psd813f2v STMicroelectronics, psd813f2v Datasheet - Page 67

• Manufacturer Part Number: psd813f2v
• Description: Flash In-system Programmable Isp Peripherals For8-bits Mcus, 3v
• Manufacturer: STMicroelectronics

RESET TIMING AND DEVICE STATUS AT RESET
Power-Up Reset
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration t
steady. During this period, the device loads inter-
nal configurations, clears some of the registers
and sets the Flash memory into Operating mode.
After the rising edge of Reset (RESET), the PSD
remains in the Reset mode for an additional peri-
od, t
lowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR, CNTL0) High, during Power On Re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Flash memory WRITE cycle initiation is prevented
automatically when V
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
t
Figure 34. Reset (RESET) Timing
NLNH
V
RESET
OPR
.
CC
, before the first memory access is al-
CC
Power-On Reset
V
is below V
t NLNH-PO
CC
(min)
NLNH-PO
LKO
after V
.
Doc ID 10552 Rev 3
t OPR
CC
is
The same t
is operational after warm reset. Figure
the timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 33., page 68
PLD status during Power On Reset, warm reset
and Power-down mode. PLD outputs are always
valid during warm reset, and they are valid in Pow-
er On Reset once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
typically long before the V
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDabel equa-
tions.
Reset of Flash Memory Erase and Program
Cycles (on the PSD834Fx)
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the Read Mode within a period of t
OPR
period is needed before the device
shows the I/O pin, register and
Warm Reset
PSD813F2V, PSD854F2V
t NLNH-A
t NLNH
CC
ramps up to operat-
NLNH-A
t OPR
AI02866b
34
.
shows
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