sg6741a Fairchild Semiconductor, sg6741a Datasheet
sg6741a
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sg6741a Summary of contents
Page 1
... PWM output is disabled until V limit, when the controller starts up again. As long as V exceeds ~26V, the internal OVP circuit is triggered. SG6741A is available in an 8-pin SOP package. Package 8-Lead Small Outline Package (SOP) 8-Lead Small Outline Package (SOP) ...
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... Application Diagram Block Diagram © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0.1 Figure 1. Typical Application Figure 2. Block Diagram 2 www.fairchildsemi.com ...
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... VDD OVP trigger point. 8 GATE Driver Output. Totem-pole output driver. Soft driving waveform is implemented for improved EMI. © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0 SOP P: Z =Lead Free Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location F: Fairchild logo ...
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... All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0.1 Parameter ( ＜50°C) ...
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... The Delay Time of FB Pin Open- t D-OLP Loop Protection V Green-Mode Entry FB Voltage FB-N V Green-Mode Ending FB Voltage FB-G V Zero Duty-Cycle Input Voltage FB-ZDC © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0.1 Conditions V – 0.16V DD-ON V =15V, GATE Open DD V +0.1V DD-OLP Auto Restart Auto Restart V =90V, (V ...
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... Gate High Voltage GATE-H tr Gate Rising Time tf Gate Falling Time I Gate Source Current GATE-SOURCE V Gate Output Clamping Voltage GATE-CLAMP DCY Maximum Duty Cycle MAX © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0.1 (Continued FB-ZDC FB-G FB-N Figure 5. PWM Frequency Conditions V –V STHFL STHVA V =15V, I ...
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... Figure 10. Supply Current Drawn from HV Pin (I vs. Temperature Temperature (°C ) Figure 12. Frequency in Nominal Mode (f vs. Temperature © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0 110 125 ) vs. Temperature Figure 7. Operating Supply Current (I DD-ST 13 ...
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... The range of the PWM oscillation frequency is designed as 47kHz ~ 109kHz. Current Sensing and PWM Current Limiting Peak-current-mode control is utilized in SG6741A to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current sense signal and V feedback voltage ...
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... Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the SG6741A, and increasing the begins decreasing. DD power MOS gate resistance improve performance. ...
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... EC 470µF/25V C9 EC 22µF/50V C10 CC 470pF/50V C11 CC 222pF/50V C12 CC 103pF/50V D1 Zener Diode 15V 1/2W (option) D2 BYV95C D3 FR103 F1 FUSE 4A/250V L1 900µH Q1 STP20-100CT © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0.1 BD1 VZ1 SG6741A C9 8 ...
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... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation SG6741A • Rev. 1.0.1 5.00 4.80 A 3.81 ...
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... Fairchild Semiconductor Corporation SG6741A • Rev. 1.0.1 12 www.fairchildsemi.com ...