ml4826cs-2 Fairchild Semiconductor, ml4826cs-2 Datasheet - Page 11

• Manufacturer Part Number: ml4826cs-2
• Description: Ml4826 Pfc And Dual Output Pwm Controller Combo
• Manufacturer: Fairchild Semiconductor

There are a number of different ways to supply V
ML4826. The method suggested in Figure 5, is one which
keeps the ML4826 I
a loosely regulated bootstrap winding. By feeding external
gate drive components from the base of Q1, the constant cur-
rent source does not have to account for variations in the gate
drive current. This helps to keep the maximum I
ML4826 to a minimum. Also, the current available to charge
the bootstrap capacitor from the bootstrap winding is not
limited by the constant current source. The circuit guarantees
that the maximum operating current is available at all times
and minimizes the worst case power dissipation in the IC.
Other methods such as a simple series resistor are possible,
but can very easily lead to excessive I
ML4826. Figures 6 and 7 show other possible methods for
feeding V
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
PRODUCT SPECIFICATION
REV. 1.0.5 2/14/02
CC
.
x Former
I
SENSE
CC
current to a minimum, and allows for
T3
200:1
4 x IN4148
Figure 4. Slope Compensation and Current Sense
CC
220pF
current in the
C26
PN2222
Q14
D1
CC
CC
of the
R16
471Ω
to the
U2
R21
8.63kΩ
C11
1000pF
2.2kΩ
R13
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
8 shows a typical trailing edge control scheme.
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 9 shows a leading
edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple volt-
age generated by the switching action. With such synchro-
nized switching, the ripple voltage of the first stage is
reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
10.0kΩ
47.0kΩ
R40
R38
17
18
11
10
7
9
6
V
V
R
RAMP2
AGND
DC I
V
CC
REF
DC
T
C
LIMIT
T
1V
1.5V
PWM CMP
DC I
–
–
+
+
LIMIT
ML4826
11