W83877 Winbond Electronics Corp America, W83877 Datasheet - Page 42

• Manufacturer Part Number: W83877
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

3.0 IDE
The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller
resides on the IDE hard disk drive. So the IDE interface provides only chip select signals and AT bus
signals between the IDE hard disk drive and ISA slot. Table 3-1 shows the IDE registers and their ISA
addresses.
Table 3-1
3.1 IDE Decode Description
When the processor selects the addresses which match the ones specified in CR 21, the chip system
enables CS0 = LOW; otherwise, CS0 = HIGH. When the processor selects the address which
matches the one specified in CR22, the chip system enables CS1 = LOW; otherwise, CS1 = HIGH.
4.0 UART PORT
4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-
byte FIFOs for both receive and transmit mode.
4.2 Register Address
CS0 base address + 0
CS0 base address + 1
CS0 base address + 2
CS0 base address + 3
CS0 base address + 4
CS0 base address + 5
CS0 base address + 6
CS0 base address + 7
CS1 base address + 6
I/O ADDRESS
OFFSET
Alternate Status
Sector Number
Status Register
Cylinder HIGH
Cylinder LOW
Error Register
Data Register
SDH Register
Sector Count
READ
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REGISTERS
Command Register
Fixed Disk Control
Write-Precomp
Sector Number
Cylinder HIGH
Cylinder LOW
Data Register
SDH Register
Sector Count
WRITE
W83877F