W83877 Winbond Electronics Corp America, W83877 Datasheet - Page 71

• Manufacturer Part Number: W83877
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

These two bits and PRTMOD2 (CR9 bit7) determine the parallel port mode of the W83877 (see Table
7-1 on next page ).
Table 7-1
OSCS1, OSCS0 (Bit 1, Bit 0):
These two bits and OSCS2 (CR6 bit 6) are used to select one of the W83877F's power-down
functions. These bits may be programmed in four different ways:
When bit 0 is 1 and bit 1 is set to 0, the W83877F will stop its oscillator and enter power-down mode
immediately. The W83877F will not leave the power-down mode until either a system power-on reset
from the MR pin or these two bits are used to program the chip back to power-on state. After leaving
the power-down mode, the W83877F must wait 128 mS for the oscillator to stabilize.
(BIT 7 OF CR9)
PRTMODS2
00
01
10
11
00
01
10
11
00
00
01
0
0
0
0
1
1
1
1
W83757 Mode (Default), PRTMOD2 = 0
Default state after power-on reset. In this mode, the W83877F is fully compatible with
the W83757F/W83757AF.
Extension FDD Mode (EXTFDD), PRTMOD2 = 0
Extension Adapter Mode (EXTADP), PRTMOD2 = 0
Extension 2FDD Mode (EXT2FDD), PRTMOD2 = 0
JOYSTICK Mode, PRTMOD2 = 1
EPP Mode and SPP Mode, PRTMOD2 = 1
ECP Mode, PRTMOD2 = 1
ECP Mode and EPP Mode, PRTMOD2 = 1
Default power-on state after power-on reset (OSCS2 = 0).
OSC on, 24 MHz clock is stopped internally (OSCS2 = 1). Clock can be restarted by
clearing OSCS2.
Immediate power-down (IPD) state, OSCS2 = 0
(BIT 3 OF CR0)
PRTMOD1
0
0
1
1
0
0
1
1
(BIT 2 OF CR0)
PRTMODS0
- 71 -
0
1
0
1
0
1
0
1
Publication Release Date: January 1996
W83757
EXTFDC
EXTADP
EXT2FDD
JOYSTICK
EPP/SPP
ECP
ECP/EPP
W83877F
Revision A2