W83877 Winbond Electronics Corp America, W83877 Datasheet - Page 63

• Manufacturer Part Number: W83877
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

This register controls the extended ECP parallel port functions. The bit definitions are follows:
Bit 7-5: These bits are read/write and select the mode.
Bit 4: Read/Write (Valid only in ECP Mode)
000
001
010
011
100
101
110
111
1
0
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be
used to tri-state the data lines and reading the data register returns the value on the
data lines and not the value in the data register.
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
transmitted automatically to the peripheral using ECP Protocol. When the direction
is 1 (reverse direction) bytes are moved from the ECP parallel port and packed into
bytes in the ecpDFifo.
Selects EPP Mode. In this mode, EPP is selected if the EPP supported option is
selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
7
6
5
4
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3
2
1
0
Publication Release Date: January 1996
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
W83877F
Revision A2