W83877 Winbond Electronics Corp America, W83877 Datasheet - Page 76

• Manufacturer Part Number: W83877
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

This bit enables or disables the tri-state outputs of UARTA in power-down mode.
URBTRI (Bit 0):
This bit enables or disables the tri-state outputs of UARTB in power-down mode.
8.2.6 Configuration Register 5 (CR5), default = 00H
When the device is in Extended Function mode and EFIR is 05H, the CR5 register can be accessed
through EFDR. The bit definitions are as follows:
Bit 7-4: Reserved
ECPFTHR3-0 (bit 3-0): These four bits define the FIFO threshold for the ECP mode parallel port. The
8.2.7 Configuration Register 6 (CR6), default = 00H
When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed
through EFDR. The bit definitions are as follows:
0
1
0
1
The output pins of UARTA will not be tri-stated when UARTA is in power-down mode.
The output pins of UARTA will be tri-stated when UARTA is in power-down mode.
The output pins of UARTB will not be tri-stated when UARTB is in power-down mode.
The output pins of UARTB will be tri-stated when UARTB is in power-down mode.
default value is 0000 after power-up.
7
7
6
6
5
5
4
4
3
3
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2
2
1
1
0
0
FDCTRI
IDEPWD
FDCPWD
FIPURDWM
SEL4FDD
OSCS2
Reserved
IDETRI
ECPFTHR0
ECPFTHR1
ECPFTHR2
Reserved
Reserved
Reserved
Reserved
ECPFTHR3
W83877F