at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 132
at90pwm81-16se
Manufacturer Part Number
at90pwm81-16se
Description
8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.AT90PWM81-16SE.pdf
(323 pages)
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13.23 PSC Clock Sources
13.24 Interrupts
132
AT90PWM81
According to the architecture of the PSC synchronization which build a “daisy-chain on the PSC run sig-
nal” between the three PSC, only the fault event (mode 7) which is able to “stop” the PSC through the
PRUN bits is transmitted along this daisy-chain.
A PSC which receive its Run signal from the previous PSC transmits its fault signal (if enabled) to this
previous PSC. So a slave PSC propagates its fault events when they are configured and enabled.
PSC must be able to generate high frequency with enhanced resolution.
Each PSC has two clock inputs:
Figure 13-42. Clock selection
PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source.
PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock.
Table 13-10.
This section describes the specifics of the interrupt handling as performed in AT90PWM81.
PCLKSELn
0
0
0
0
1
1
1
1
• CLK PLL from the PLL
• CLK I/O
CLK
CLK
PLL
I/O
Output Clock versus Selection and Prescaler
PCLKSELn
PPREn1
0
0
1
1
0
0
1
1
1
0
CK
PPREn0
0
1
0
1
0
1
0
1
PRESCALER
CLK
CLKPSCn output
CLK I/O
CLK I/O / 4
CLK I/O / 32
CLK I/O / 256
CLK PLL
CLK PLL / 4
CLK PLL / 32
CLK PLL / 256
PSCn
PPREn1/0
7734M–AVR–03/10
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