at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 28

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
Table 6-1.
28
Device Clocking Option
External Clock
PLL output divided by 4 : 16 MHz driven by internal RC
Calibrated Internal RC Oscillator 8 MHz
Internal 128 kHz RC Oscillator (WD)
PLL output divided by 4 / PLL driven by External
Crystal/Ceramic Resonator
PLL output divided by 4/ PLL driven by External clock
Calibrated Internal RC Oscillator 1MHz
External Crystal/Ceramic Resonator (3.0 - 8.0 MHz)
External Crystal/Ceramic Resonator (0.9 - 3.0 MHz)
External Crystal/Ceramic Resonator (0.9 - 3.0 MHz)
External Crystal/Ceramic Resonator (3.0 - 8.0 MHz)
External Crystal/Ceramic Resonator (3.0 - 8.0 MHz)
Clock Sources
AT90PWM81
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
PLL Clock – clk
ADC Clock – clk
Device Clocking Options Select
I/O
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of
such modules are the General Purpose Register File, the Status Register and the Data memory holding the
Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and
calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used
by the External Interrupt module, but note that some external interrupts are detected by asynchronous
logic, allowing such interrupts to be detected even if the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously
with the CPU clock.
PLL
The PLL clock allows the PSC modules to be clocked directly from a 64/32 MHz clock. A 16 MHz clock
is also derived for the CPU.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order
to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
The device has the following clock source options, selectable by Flash Fuse bits (default) or by the CLK-
SELR register (dynamic clock switch circuit) as shown below. The clock from the selected source is input
to the AVR clock generator, and routed to the appropriate modules.
CPU
ADC
FLASH
(1)
, PLL source and PE1 and PE2 functionality
System
Clock
Ext Clk
PLL / 4
RC Osc
WD
PLL / 4
PLL / 4
RC Osc
Ext Osc
Ext Osc
Ext Osc
Ext Osc
Ext Osc
PLL Input
RC Osc
RC Osc
RC Osc
N/A
Ext Osc
Ext Clk
RC Osc
N/A
Ext Osc
RC Osc
RC Osc
RC Osc
(2)
CKSEL3..0
CSEL3..0
1000
1001
1010
1011
0111
0000
0001
0010
0011
0101
0110
0100
b
b
b
b
b
(4)
(3)
XTAL1
XTAL1
XTAL1
XTAL1
XTAL1
XTAL1
CLKI
CLKI
PE1
I/O
I/O
I/O
I/O
7734M–AVR–03/10
XTAL2
XTAL2
XTAL2
XTAL2
XTAL2
XTAL2
PE2
I/O
I/O
I/O
I/O
I/O
I/O