at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 178

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

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178
AT90PWM81
PSCR Interrupt Flag Register – PIFR0
When this bit is set, an external event which can generates a capture from Retrigger/Fault block A gener-
ates also an interrupt.
• Bit 2 – Reserved
• Bit 1– PEOEPE0 : PSCR End Of Enhanced Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reduced reaches the end of the 15th PSC cycle.
This allows to update the PSCR values in the interrupt routine and to start a new enhanced cycle with the
new values at the next PSCR cycle end.
• Bit 0 – PEOPE0 : PSCR End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSCR reaches the end of the whole cycle.
Bit
Read/Write
Initial Value
• Bit 7 – POAC0B : PSCR Output B Activity
This bit is set by hardware each time the output PSCOUT01 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSCR output doesn’t change due to a frozen external input signal.
• Bit 6 – POAC0A : PSCR Output A Activity
This bit is set by hardware each time the output PSCOUT00 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSCR output doesn’t change due to a freezen external input signal.
• Bit 5 – Reserved
• Bit 4 – PEV0B : PSCR External Event B Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block B occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE0B bit = 0).
• Bit 3 – PEV0A : PSCR External Event A Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block A occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE0A bit = 0).
• Bit 2:1 – PRN01:0 : PSCR Ramp Number
7
POAC0B
R
0
6
POAC0A
R
0
5
-
R
0
4
PEV0B
R/W
0
3
PEV0A
R/W
0
2
PRN01
R
0
1
PRN00
R
0
0
PEOP0
R/W
0
7734M–AVR–03/10
PIFR0