at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 83

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

11.0.2
11.0.3
7734M–AVR–03/10
External Interrupt Mask Register – EIMSK
External Interrupt Flag Register – EIFR
Note:
• Bits 2..0 – INT2 – INT0: External Interrupt Request 3 - 0 Enable
When an INT2 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the cor-
responding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt
Control Register – EICRA – defines whether the external interrupt is activated on rising or falling edge or
level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an
output. This provides a way of generating a software interrupt.
• Bits 2..0 – INTF2 - INTF0: External Interrupt Flags 3 - 0
When an edge or logic change on the INT2:0 pin triggers an interrupt request, INTF2:0 becomes set (one).
If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are set (one), the MCU
will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively,
the flag can be cleared by writing a logical one to it. These flags are always cleared when INT2:0 are con-
figured as level interrupt.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
1. n = 3, 2, 1 or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit
in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
7
-
R/W
0
7
-
R/W
0
6
-
R/W
0
6
-
R/W
0
5
-
R/W
0
5
-
R/W
0
4
-
R/W
0
4
-
R/W
0
3
-
R/W
0
3
-
R/W
0
2
INT2
R/W
0
2
INTF2
R/W
0
1
INT1
R/W
0
1
INTF1
R/W
0
AT90PWM81
0
IINT0
R/W
0
0
IINTF0
R/W
0
EIMSK
EIFR
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