at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 187

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

15.5.2
7734M–AVR–03/10
SPI Status Register – SPSR
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS
is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR
will become set. The user will then have to set MSTR to re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when
idle. Refer to
Table 15-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing
(last) edge of SCK. Refer to
marized below:
Table 15-4.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect
on the Slave. The relationship between SCK and the clk
Table 15-5.
Bit
SPI2X
0
0
0
0
1
1
1
1
Figure 15-3
CPOL
CPHA
7
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
0
1
0
1
6
and
Figure 15-3
SPR1
Figure 15-4
0
0
1
1
0
0
1
1
5
and
for an example. The CPOL functionality is summarized below:
Leading Edge
Leading Edge
Figure 15-4
4
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
3
IO
for an example. The CPOL functionality is sum-
frequency f
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
2
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
clkio
is shown in the following table:
1
AT90PWM81
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
0
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