at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 72

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

10.3.1
72
AT90PWM81
MCU Control Register – MCUCR
Table 10-2.
The following subsections shortly describe the alternate functions for each port, and relate the overriding
signals to the alternate function. Refer to the alternate function description for further details.
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn
Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). Se
Bit
Read/Write
Initial Value
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
7
–
R
0
Generic Description of Overriding Signals for Alternate Functions
Full Name
Pull-up Override
Enable
Pull-up Override
Value
Data Direction
Override Enable
Data Direction
Override Value
Port Value Override
Enable
Port Value Override
Value
Port Toggle Override
Enable
Digital Input Enable
Override Enable
Digital Input Enable
Override Value
Digital Input
Analog Input/Output
R
6
–
0
5
–
R
0
Description
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when {DDxn,
PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD
Register bits.
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is enabled by
the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when DDOV is
set/cleared, regardless of the setting of the DDxn Register bit.
If this signal is set and the Output Driver is enabled, the port value is
controlled by the PVOV signal. If PVOE is cleared, and the Output
Driver is enabled, the port Value is controlled by the PORTxn
Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the setting
of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by the DIEOV
signal. If this signal is cleared, the Digital Input Enable is determined
by MCU state (Normal mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is
set/cleared, regardless of the MCU state (Normal mode, sleep mode).
This is the Digital Input to alternate functions. In the figure, the signal
is connected to the output of the schmitt trigger but before the
synchronizer. Unless the Digital Input is used as a clock source, the
module with the alternate function will use its own synchronizer.
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
4
PUD
R/W
0
3
RSTDIS
RW
0
2
CKRC81
R/W
0
1
IVSEL
R/W
0
0
IVCE
R/W
0
7734M–AVR–03/10
MCUCR