at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 38

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

10.4.4
10.4.5
10.4.6
38
AT91SAM9260
Serial Synchronous Controller
Timer Counter
Multimedia Card Interface
The USART contains features allowing management of the Modem Signals DTR, DSR, DCD
and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0,
DSR0, DCD0 and RI0.
The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1
and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features.
Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpre-
dictable results. In these USARTs, the commands relating to the Modem Mode have no effect
and the status bits relating the status of the modem signals are never activated.
Note:
• Test Modes
• Provides serial synchronous communication links used in audio and telecom applications
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
• Two blocks of three 16-bit Timer Counter channels
• Each channel can be individually programmed to perfom a wide range of functions including:
• Each channel is user-configurable and contains:
• Each block contains two global registers that act on all three TC Channels
• One double-channel MultiMedia Card Interface
• Compatibility with MultiMedia Card Specification Version 3.11
(with CODECs in Master or Slave Modes, I
different event on the frame sync signal
signal
– Communication at up to 115.2 Kbps
– Remote Loopback, Local Loopback, Automatic Echo
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See
Figure 8-1, “AT91SAM9260 Memory Mapping,” on page 21
base addresses.
2
S, TDM Buses, Magnetic Card Reader, etc.)
for TC Block 0 and TC Block 1
6221G–ATARM–31-Jan-08