at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 97
at91sam9260-cj
Manufacturer Part Number
at91sam9260-cj
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9260-CJ.pdf
(790 pages)
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14.3.6
Figure 14-9.
6221G–ATARM–31-Jan-08
if (URSTEN = 0) and
Peripheral Access
Reset Controller Status Register
(URSTIEN = 1)
Reset Controller Status and Interrupt
URSTS
NRSTL
rstc_irq
NRST
MCK
The Reset Controller status register (RSTC_SR) provides several status fields:
resynchronization
• When in Watchdog Reset:
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR
further software reset should be performed until the end of the current one. This bit is
automatically cleared at the end of the current software reset.
each MCK rising edge.
register. This transition is also detected on the Master Clock (MCK) rising edge (see
14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the
URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the
RSTC_SR status register resets the URSTS bit and clears the interrupt.
2 cycle
– The processor reset is active and so a Software Reset cannot be programmed.
– A User Reset cannot be entered.
resynchronization
2 cycle
RSTC_SR
read
AT91SAM9260
Figure
97
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