at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 777

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Table 44-1.
6221G–ATARM–31-Jan-08
Revision
6221D
Current version appears first
Comments
RSTC: In
information on startup counter for crystal oscillator.
EBI: Corrected number of CS to 7 in
Table 20-1, “EBI I/O Lines Description,” on page
External Static Devices Connections,” on page 143
External Device Connections,” on page
Added note
page
SMC: Added information on boot in
169.
SDRAMC: Change to
page
ECC:
Section 23.3.1 ”Write Access”
updated.
Section 23.4.4 ”ECC Parity Register”, on page 243
NParity Register”, on page 243
PMC: Updated
page 257
Updated
Updated information on enable/disable in
Controller”, on page
PIO:
Logic.
Section 29.4.5 “Synchronous Data Output” on page
corrected.
Section 29.6 “Parallel Input/Output Controller (PIO) User Interface” on page
footnotes updated on PIO_PSR, PIO_ODSR, PIO_PDSR in Register Mapping
table.
SSC: Defined max Frame Sync Data length in
on page
TC: Added information on compare register B and waveform generation in
34.5.12 “External Event/Trigger Conditions” on page
Register Bit
Channel Mode Register: Waveform Mode”
Added
chaining.
EMAC:
”Interrupt Disable Register” on page
”Interrupt Mask Register” on page
UHP: Corrected signal name in block diagram
Updated schematic
Controller” on page 659
659.
Figure 29-3, ”I/O Line Control Logic” on page 336
144.
214; addition of note
Section 23.3 ”Functional Description”, on page 235
Figure 34-2, ”Clock Chaining Selection” on page 519
”Interrupt Enable Register” on page
502.
Section 25.4.1 ”Main Oscillator Connections”, on page
Section 14.3.1 “Reset Controller Overview” on page 89
and
(3)
Description“EEVT: External Event Selection” on page 538
to
Figure 25-3 ”Typical Crystal Connection” on page
Figure 25-1 ”Typical Slow Clock Crystal Oscillator Connection” on
Table 20-4, “EBI Pins and External Device Connections,” on
Figure 37-4 ”Board Schematic to Interface UHP Device
263.
Step 5
and updated
(1)
in
on
and
Section 22.4.1 ”SDRAM Device Initialization” on
Instruction updated.
page
611, access changed to Read-only.
Section 23.3.2 ”Read Access”, on page 236
Section 21.7.2.1 “Byte Write Access” on page
610, access changed to Write-only.
Section 20.1 “Description” on page
Section 37.5 ”Typical Connection” on page
214.
144.
Section 26.3 ”Processor Clock
to further clarify.
609, access changed to Write-only.
Section 33.6.5.1 ”Frame Sync Data”
Figure 37-1 on page 655
141,
and
and
338, PIO_OWSR typo
530. Added Note
Table 20-3, “EBI Pins and
change to I/O Line Control
Section 23.4.5 ”ECC
Table 20-4, “EBI Pins and
updated.
to demonstrate clock
258.
258.
added
(1)
in
to UHPCK.
139,
to
“TC
Section
342,
AT91SAM9260
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