at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 57

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

11.7.1
Table 11-7.
11.7.2
11.7.3
6221G–ATARM–31-Jan-08
HBurst[2:0]
SINGLE
INCR4
INCR8
WRAP8
Supported Transfers
Thumb Instruction Fetches
Address Alignment
Supported Transfers
Description
Single transfer
Four-word incrementing burst
Eight-word incrementing burst
Eight-word wrapping burst
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or
bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into
packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not
support split and retry requests.
Table 11-7
are used for.
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses
on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the
necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses
are aligned to word boundaries.
gives an overview of the supported transfers and different kinds of transactions they
Single transfer of word, half word, or byte:
Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,
NCB, WT, or WB write.
Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
Cache linefill
• data write (NCNB, NCB, WT, or WB that has missed in DCache)
• data read (NCNB or NCB)
• NC instruction fetch (prefetched and non-prefetched)
• page table walk read
AT91SAM9260
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