at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 390

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 31-6. Master Write with One Data Byte
Figure 31-7. Master Write with Multiple Data Byte
Figure 31-8. Master Write with One Byte Internal Address and Multiple Data Bytes
31.7.5
390
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
AT91SAM9260
Master Receiver Mode
S
Write THR (Data n)
S
DADR
TXCOMP
DADR
TXRDY
TWD
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
W
Write THR (DATA)
S
W
A
DADR
IADR(7:0)
A
Write THR (Data n+1)
DATA n
W
A
A
DATA n
Write THR (Data n+1)
A
DATA
A
Write THR (Data n+x)
DATA n+5
Last data sent
(ACK received and TXRDY = 1)
A
STOP sent automaticaly
Write THR (Data n+x)
DATA n+5
Last data sent
P
A
A
DATA n+x
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
Figure
6221G–ATARM–31-Jan-08
A
31-9. When the
A
P
P