at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 769

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.3.5.2
44.3.6
44.3.6.1
44.3.6.2
44.3.6.3
6221G–ATARM–31-Jan-08
Serial Synchronous Controller (SSC)
Baudrate set to 1
Unexpected RK clock cycle when RK outputs a clock during data transfer
Incorrect first RK clock cycle when RK outputs a clock during data transfer
Transmitter Limitations in Slave Mode
then an additional pulse will be generated on output PSCK during the second transfer.
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
When Baudrate is set to 1 (i.e., when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No error occurs if BITS field
equals 8,10,12,14 or 16 and Baudrate = 1.
None.
When the SSC receiver is used in the following configuration:
then, at the end of the data, the RK pin is set in high impedance which may be interpreted as an
unexpected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used in the following configuration:
then the first clock cycle time generated by the RK pin is equal to MCK/(2 x (DIV +1)) instead of
MCK/(2 x DIV).
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro has a Start Delay equal to zero.
None.
• transmit with the slowest chip select and then with the fastest one
• the internal clock divider is used (CKS = 0 and DIV different from 0),
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9260
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