lpc2888fet180 NXP Semiconductors, lpc2888fet180 Datasheet - Page 18

• Manufacturer Part Number: lpc2888fet180
• Description: 16/32-bit Arm Microcontrollers; 8 Kb Cache, Up To 1 Mb Flash, Hi-speed Usb 2.0 Device, And Sdram Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2880_LPC2888_2
Preliminary data sheet
6.9.1 Features
6.10 Watchdog timer
6.9 General purpose timers
All 99 Pending signals are presented to each of the five output logic blocks. Each output
logic block includes a set of four Interrupt Output Mask Registers, each set totalling 99
bits, that control whether each signal applies to that output. These are logically ANDed
with the corresponding Pending signals, and the 99 results in each logic block are logically
ORed to make the output of the block. The 496 results can be read in the Interrupt Output
Pending Registers.
Outputs 0 thru 3 are routed to the Interrupt Controller, in which each can be individually
enabled to cause an interrupt. Output 4 is routed to the Clock Generation Unit, in which it
can serve to enable clocking for selected clock domains. The five outputs can be read in
the Output Register.
The LPC2880/2888 contains two fully independent general purpose timers. Each timer is
a 32 bit wide down counter with a selectable prescaler. The prescaler allows either the
system clock to be used directly, or the clock to be divided by 16 or 256.
Two modes of operation are available, free-running and periodic timer. In periodic timer
mode, the counter will generate an interrupt at a constant interval. In free-running mode
the timer will overflow after reaching its zero value and continue to count down from the
maximum value.
The purpose of the watchdog timer is to interrupt and/or reset the microcontroller within a
reasonable amount of time if it enters an erroneous state. When enabled, the watchdog
will generate an interrupt or a system reset if the user program fails to reset the watchdog
within a predetermined amount of time. Alternatively, it can be used as an additional
general purpose Timer.
The WDT clock increments a 32-bit Prescale Counter, the value of which is continually
compared to the value of the Prescale Register. When the Prescale Counter matches the
Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit
Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the
value in the Prescale Register plus one.
The value of the Timer Counter is continually compared to the values in two registers
called Match Register 0 and 1. When/if the value of the Timer Counter matches that of
Match Register 0 at a WDT clock edge, a signal ‘m0’ can be asserted to the Event Router,
which can be programmed to send an interrupt signal to the Interrupt Controller as a
result. When/if the value of the Timer Counter matches that of Match Register 1 at a WDT
clock edge, a signal ‘m1’ can be asserted to the CGU, which resets the chip as a result.
The CGU also includes a flag to indicate whether a reset is due to a watchdog time-out.
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Two independent 32-bit timers.
Free-running or periodic operating modes.
Generate timed interrupts.
Rev. 02 — 21 November 2006
16/32-bit ARM microcontrollers with external memory interface
LPC2880; LPC2888
© NXP B.V. 2006. All rights reserved.
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