lpc2888fet180 NXP Semiconductors, lpc2888fet180 Datasheet - Page 24

• Manufacturer Part Number: lpc2888fet180
• Description: 16/32-bit Arm Microcontrollers; 8 Kb Cache, Up To 1 Mb Flash, Hi-speed Usb 2.0 Device, And Sdram Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2880_LPC2888_2
Preliminary data sheet
6.20.5 Power control and modes
6.20.6 APBs
6.21 Emulation and debugging
The low power PLL takes the input clock and multiplies it up to a higher frequency (by 1 to
32), then divides it down (by 1, 2, 4, or 8) to provide the output clock used by the CGU.
The output frequency of this PLL can range from 10 MHz to 320 MHz. Functional blocks
may have limitations below this upper limit.
The high-speed PLL takes the input clock, optionally divides it down (by 1 to 256), then
multiplies it up to a higher frequency (by 1 to 1024), then divides it down (by 1 to 16) to
provide the output clock used by the CGU. The output frequency of this PLL can range
from 4.3 MHz to 550 MHz. Functional blocks may have limitations below this upper limit.
Power control on the LPC2880/2888 is accomplished by detailed control over the clocking
of each functional block via the CGU. The LPC2880/2888 includes a very versatile
clocking scheme that provides a great deal of control over performance and power usage.
On-chip functions are divided into 11 groups. Each group has a selection for one of
several basic clock sources. Graceful (glitch-free) switching between these clock sources
is provided.
Three of these functional groups include one fractional divider that allows any rate below
the selected clock to be derived. Three other functional groups include more than one
fractional divider, allowing several different slower clocks to be generated within the group.
Each function within the group can then be assigned to use any one of the generated
clocks.
Each function within any group can also be individually turned off by disabling the clock to
that function. When added to the versatile clock rate selection, this allows very detailed
control of power utilization.
Each function also can be configured to have clocks automatically turned on and off
based on a signal from the Event Router.
Most peripheral functions are accessed by on-chip APBs that are attached to the higher
speed AHB. The APBs perform reads and writes to peripheral registers in three peripheral
clocks.
The LPC2880/2888 supports emulation via a dedicated JTAG serial port. The dedicated
JTAG port allows debugging of all chip features without impact to any pins that may be
used in the application.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the
Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
Rev. 02 — 21 November 2006
16/32-bit ARM microcontrollers with external memory interface
LPC2880; LPC2888
© NXP B.V. 2006. All rights reserved.
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