lpc2888fet180 NXP Semiconductors, lpc2888fet180 Datasheet - Page 21

• Manufacturer Part Number: lpc2888fet180
• Description: 16/32-bit Arm Microcontrollers; 8 Kb Cache, Up To 1 Mb Flash, Hi-speed Usb 2.0 Device, And Sdram Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2880_LPC2888_2
Preliminary data sheet
6.16.1 Features
6.16 Analog I/O
6.17 USB 2.0 high-speed device controller
The analog I/O system includes an I
dual ADC, and a dual DAC. Each channel includes a separate 4 sample FIFO.
Each of the two ADC inputs is connected to a Programmable Gain Amplifier (PGA).
Each DAC has two output pins.
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host schedules transactions in 1 ms frames. Each frame contains an SOF marker and
transactions that transfer data to/from device endpoints. There are 4 types of transfers
defined for the endpoints. Control transfers are used to configure the device. Interrupt
transfers are used for periodic data transfer. Bulk transfers are used when rate of transfer
is not critical. Isochronous transfers have guaranteed delivery time but no error correction.
The LPC2880/2888 USB controller enables 480 Mbit/s or 12 Mbit/s data exchange with a
USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0 ATX
physical interface.
The USB controller consists of the protocol engine and buffer management blocks. It
includes an SRAM that is accessible to the DMA engine and to the processor via the
register interface.
The DMA engine is an AHB master, having direct access to all of ARM memory space but
particularly to on-chip RAM. Each USB endpoint that requires its data to be transferred via
DMA is allocated to a logical DMA channel in the DMA engine.
Endpoints with small packet sizes can be handled by software via registers in the USB
controller. In particular, Control Endpoint 0 is always handled in this way.
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Input multiplexing among 5 pins.
Power-down mode.
Measurement range 0 V to 3.3 V.
10-bit conversion time
Single or continuous conversion mode.
I
I
Dual 16-bit ADCs with individual inputs routed through programmable gain amplifiers.
Input takes place through a 4 sample FIFO.
Dual 16-bit DACs. Each DAC has its own output pin. Output takes place through a 4
sample FIFO.
2
2
S-bus input channel with a 4 sample FIFO for stereo Digital Analog Input (DAI).
S-bus output channel with a 4 sample FIFO for stereo Digital Analog Output (DAO).
Rev. 02 — 21 November 2006
16/32-bit ARM microcontrollers with external memory interface
2.44 s.
2
S-bus input channel, an I
LPC2880; LPC2888
2
S-bus output channel, a
© NXP B.V. 2006. All rights reserved.
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