z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 187

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
Slave Transactions
16. The I
17. The I
18. The I
19. The I
20. The I
21. The I
22. The software responds by reading the I
23. The I
24. If there are more bytes to transfer, the I
25. The I
26. The software responds by setting the
27. A
The following sections describe Read and Write transactions to the I
ured for 7-bit and 10-bit slave modes.
Slave Address Recognition
The following slave address recognition options are supported.
Slave 7-Bit Address Recognition Mode—
controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the
hardware detects a match to the 7-bit slave address defined in the I2CSLVAD register and
generates the slave address match interrupt (
The I
in the
Slave 10-Bit Address Recognition Mode—
controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the hard-
ware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD
registers and generates the slave address match interrupt (the
sends the
tion is complete, and the following steps can be ignored.
register (the third address transfer).
slave read address and a 1 (Read).
High period of SCL.
the final byte, the software must set the
on the value of the
2
NAK
STOP
C controller automatically responds during the Acknowledge phase with the value
2
2
2
2
2
2
2
2
C controller sends a repeated
C controller loads the I
C controller sends
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller shifts in a byte of data from the slave.
C controller asserts the Receive interrupt.
C controller sends an Acknowledge or Not Acknowledge to the I
C controller generates a NAK interrupt (the
bit of the I2CCTL register.
condition is sent to the I
STOP
condition on the bus, and clears the
NAK
bit.
11110b
2
C Shift register with the contents of the I
2
, followed by the two most-significant bits of the
C slave.
START
STOP
2
2
If
C Data register. If the next data byte is to be
NAK
C controller returns to Step 18.
If
the SAM
IRM
condition.
bit of the I
IRM
bit of the I
= 0 during the address phase and the
= 0 during the address phase and the
NCKI
bit = 1 in the I2CISTAT register).
STOP
2
C Control register.
2
C Control register.
bit in the I2CISTAT register).
SAM
and
Product Specification
bit = 1 in the I2CISTAT
NCKI
2
C controller config-
bits. The transac-
Slave Transactions
2
2
C slave, based
C Data
175