z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 256

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
Caution:
OCDCNTR Register
on which it was previously looping, it automatically sets the DBGMODE bit and enters
DEBUG mode.
The majority of the OCD commands remain disabled when the eZ8 CPU is looping on a
BRK instruction. The eZ8 CPU must be in DEBUG mode before these commands are
issued.
Break Points in Flash Memory
The BRK instruction is Opcode
a byte in Flash memory. To implement a break point, write
overwriting the current instruction. To remove a break point, erase the corresponding page
of Flash memory and reprogram with the original data.
The OCD contains a multipurpose 16-bit Counter register which can be used for the
following:
•
•
•
When configured as a counter, the OCDCNTR register starts counting when the on-chip
debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or
when it reaches the maximum count of
resets itself to
cycles between break points.
If the OCDCNTR register is configured to generate a BRK when it counts down to zero, it
will not be reset when the CPU starts running. Once the OCD exits DEBUG mode, the
counter starts counting down toward zero. If the OCD enters DEBUG mode before the
OCDCNTR register counts down to zero, the OCDCNTR stops counting.
If the OCDCNTR register is configured to generate a BRK when the program counter
matches the OCDCNTR register, the OCDCNTR register will not be reset when the CPU
resumes executing and it will not be decremented when the CPU is running. A BRK is
generated when the program counter matches the value in the OCDCNTR register before
executing the instruction at the location of the program counter.
The OCDCNTR register is used by many OCD commands. It counts the number of bytes for
the register and memory read/write commands. It retains the residual value when generat-
ing the CRC. If the OCDCNTR is used to generate a BRK, its value must be written as a
final step before leaving DEBUG mode.
Count system clock cycles between break points
Generate a BRK when it counts down to 0
Generate a BRK when its value matches the Program Counter
0000h
when the OCD exits DEBUG mode, if it is configured to count clock
00h
, which corresponds to the fully programmed state of
FFFFh
. The OCDCNTR register automatically
Z8FMC16100 Series Flash MCU
00h
to the appropriate address,
Product Specification
OCDCNTR Register
244