z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 55
z8fmc16100
Manufacturer Part Number
z8fmc16100
Description
Z8 Encore Motor Control Flash Mcus
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z8FMC16100.pdf
(381 pages)
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Table 21. Port A–C High Drive Enable Subregisters
Table 22. Port A–C STOP Mode Recovery Source Enable Subregisters
BITS
FIELD
RESET
R/W
ADDR
Port A–C Pull-Up Enable Subregisters
PS024611-0408
BITS
FIELD
RESET
R/W
ADDR
Bit Position
[7:0]
PHDE
PSMRE7
PHDE7
R/W
R/W
7
0
7
0
If 05H in Port A–C Address register, accessible through the Port A–C Control register
Port A–C High Drive Enable Subregisters
The Port A–C High Drive Enable subregisters
C Control registers by writing
the Port A–C High Drive Enable subregisters to 1 configures the specified port pins for
high current output drive operation. The Port A–C High Drive Enable subregisters affect
the pins directly. As a result, alternate functions are also affected.
If 04H in Port A-C Address register, accessible through the Port A-C Control register
Port A–C Stop Mode Recovery Source Enable Subregisters
The Port A–C Stop Mode Recovery Source Enable subregisters
through the Port A–C Control registers by writing
Setting the bits in the Port A–C Stop Mode Recovery Source Enable subregisters to 1
configures the specified port pins as a Stop Mode Recovery source. During STOP mode,
any logic transition on a port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
Value (H)
0
1
PSMRE6
PHDE6
R/W
R/W
6
0
6
0
Description
Port High Drive Enable
The Port pin is configured for standard output current drive.
The Port pin is configured for high output current drive.
PSMRE5
PHDE5
R/W
R/W
5
0
5
0
04h
PSMRE4
PHDE4
R/W
R/W
4
0
4
0
to the Port A–C Address registers. Setting the bits in
PSMRE3
PHDE3
R/W
R/W
(Table
3
0
3
0
05h
Z8FMC16100 Series Flash MCU
21) are accessed through the Port A-
PSMRE2
to the Port A-C Address registers.
PHDE2
R/W
R/W
2
0
2
0
Product Specification
Port A–C Control Registers
(Table
PSMRE1
PHDE1
R/W
R/W
1
0
1
0
22) are accessed
PSMRE0
PHDE0
R/W
R/W
0
0
0
0
43
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