z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 37

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
Stop Mode Recovery
External Reset Indicator
On-Chip Debugger Initiated Reset
Fault Detect Logic Reset
continues to be held in the Reset state. If the RESET pin is held Low beyond the System
Reset timeout, the device exits the Reset state 16 system clock cycles following RESET
pin deassertion. If the RESET pin is released before the System Reset timeout, the RESET
pin is driven Low by the chip until the completion of the timeout as described in the next
section. In STOP mode the digital filter is bypassed because the System Clock is disabled.
Following a System Reset initiated by the external RESET pin, the EXT status bit in the
Reset Status and Control Register
During System Reset, the RESET pin functions as an open-drain (active Low) reset mode
indicator in addition to the input functionality. This reset output feature allows a
Z8FMC16100 Series Flash MCU device to reset other connected components , even if the
reset is caused by internal sources such as POR, VBO, or WDT events and as an indication
of when the reset sequence completes.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in
A System Reset may be initiated through the OCD by setting
register. The OCD is not reset but the rest of the chip goes through a normal System Reset.
The
POR
Fault detect circuitry exists to detect illegal state changes which may be caused by
transient power or electrostatic discharge events. When such a fault is detected, a system
reset is forced. Following the system reset, the
Register
The STOP mode is entered by execution of a
detailed STOP mode information, see
Recovery, the device is held in reset for 66 cycles of the IPO. Stop Mode Recovery only
affects the contents of the
ter. Stop Mode Recovery does not affect any other values in the Register File, including
the Stack Pointer, Register Pointer, Flags, peripheral control registers, and general-
purpose RAM.
RST
bit in the
Table 6
is set.
bit automatically clears during the system reset. Following the system reset, the
Reset Status and Control Register
has elapsed.
Reset Status and Control Register
is set to 1.
Low-Power Modes
is set.
FLTD
STOP
bit in the
instruction by the eZ8 CPU. For
on page 29. During Stop Mode
and
RST
Product Specification
Reset Status and Control
Oscillator Control Regis-
bit of the OCDCTL
External Reset Indicator
25