w77e58 Winbond Electronics Corp America, w77e58 Datasheet - Page 14

• Manufacturer Part Number: w77e58
• Description: 8 Bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

TIMER CONTROL
TF1:
TR1:
TF0:
TR0:
IE1:
IT1:
IE0:
IT0:
TIMER MODE CONTROL
GATE: Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high
C T
/
: Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
, the timer counts high-to-low edges of the Tx pin.
Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
Mnemonic: TCON
Mnemonic: TMOD
Bit:
Bit:
GATE
TF1
7
7
C T
TR1
6
6
/
TIMER1
TF0
M1
- 14 -
5
5
TR0
M0
4
4
Preliminary W77E58
GATE
IE1
3
3
Address: 88h
Address: 89h
C T
IT1
2
2
/
TIMER0
IE0
M1
1
1
IT0
M0
0
0