w77e58 Winbond Electronics Corp America, w77e58 Datasheet - Page 50

• Manufacturer Part Number: w77e58
• Description: 8 Bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

Table 6. SFR Reset Value, continued
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
WDCON
The POR bit WDCON.6 is set only by the power on reset. The PFI bit WDCON.4 is set when the
power fail condition occurs. However, a power-on reset will clear this bit. The WTRF bit WDCON.2 is
set when the Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit
WDCON.1 is cleared by power on resets. This disables the Watchdog timer resets. A watchdog or
external reset does not affect the EWT bit.
INTERRUPTS
The W77E58 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts
can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON or EXIF is set. The flag bit requests the interrupt. Since
the external interrupts are sampled every machine cycle, they have to be held high or low for at least
one complete machine cycle. The IEx flag is automatically cleared when the service routine is called.
If the level triggered mode is selected, then the requesting source has to hold the pin low till the
interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the service routine.
If the interrupt continues to be held low even after the service routine is completed, then the
processor may acknowledge another interrupt request from the same source. Note that the external
interrupts INT2 to INT5 are edge triggered only. By default, the individual interrupt flag corresponding
to external interrupt 2 to 5 must be cleared manually by software. It can be configured with hardware
cleared by setting the corresponding bit HCx in the T2MOD register. For instance, if HC2 is set
hardware will clear IE2 flag after program enters the interrupt 2 service routine.
SFR Name
SCON
SBUF
P2
SADDR1
SCON1
ROMMAP
EXIF
P4
External reset
0x0x0xx0b
Reset Value
00000000b
xxxxxxxx
11111111b
00000000b
00000000b
01
0000
xxxx
xxx
xxx
1111b
110b
0b
b
Watchdog reset
0x0x01x0b
- 50 -
SFR Name
B
EIP
PC
SADEN1
SBUF1
PMR
STATUS
Power on reset
01000000b
Preliminary W77E58
Reset Value
00000000b
xxx00000b
00000000b
00000000b
xxxxxxxx
010xx0x0b
000x0000b
b