w77e58 Winbond Electronics Corp America, w77e58 Datasheet - Page 21

• Manufacturer Part Number: w77e58
• Description: 8 Bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

IP.7:
PS1:
PT2:
PS:
PT1:
PX1:
PT0:
PX0:
SLAVE ADDRESS MASK ENABLE
SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When
SLAVE ADDRESS MASK ENABLE 1
SADEN1:This register enables the Automatic Address Recognition feature of the Serial port 1. When
SERIAL PORT CONTROL 1
SM0_1/FE_1: Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR
This bit is un-implemented and will read high.
This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level.
This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level.
This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level.
This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.
This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.
This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.
This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.
Bit:
a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the
incoming serial data. When SADEN.n is 0, then the bit becomes a "don't care" in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address.
a bit in the SADEN1 is set to 1, the same bit location in SADDR1 will be compared with the
incoming serial data. When SADEN1.n is 0, then the bit becomes a "don't care" in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 1. When all the bits of SADEN1 are 0, interrupt will occur for any incoming address.
determines whether this bit acts as SM0_1 or as FE_1. the operation of SM0_1 is
described below. When used as FE_1, this bit will be set to indicate an invalid stop bit.
This bit must be manually cleared in software to clear the FE_1 condition.
SM0_1/FE_1
Mnemonic: SADEN1
Mnemonic: SADEN
Mnemonic: SCON1
Bit:
Bit:
7
7
7
SM1_1
6
6
6
SM2_1
5
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5
5
REN_1
4
4
4
TB8_1
3
Preliminary W77E58
Publication Release Date: March 1999
3
3
Address: BAh
RB8_1
Address: C0h
Address: B9h
2
2
2
TI_1
1
1
1
Revision A1
RI_1
0
0
0